(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to an improved method of formation of conducting vias between successive layers of conductive interconnection patterns.
(2) Description of Related Art
The complexity of present-day integrated circuits requires multiple layers of interconnecting conductor lines in order to interconnect the many components in dense circuits. Furthermore, contacts between successive layers of interconnecting conductor lines must have very small surface area and must be spaced at very small intervals in order to achieve maximum wiring density. In order to achieve the necessary small spacing intervals the vias etched through insulating layers between successive layers of interconnecting conductor lines must have nearly vertical sidewalls and dry etching processes such as plasma etching and RIE (Reactive Ion Etching) have been developed to produce vertical sidewall vias. After formation of the vertical sidewall vias, the aspect ratio of vias is generally greater than 3 and often as high as 5 to 10. Aspect ratio is the ratio of the height to the width of the opening defining the via. The metal deposition process used to fill the vias must be capable of filling the vias with conducting metallization which is without voids within the vias. Voids within the via metallization reduce the conductivity of the via and also entrap contaminants which can degrade process yield and integrated circuit reliability. Also, the conducting metallization used to fill the vias must have sufficiently high electrical conductivity to meet the design criteria of the integrated circuits. And, the conducting metallization should be resistant to electromigration resulting from the necessity of the conducting vias to carry high current densities during circuit operation. Additionally, in such multiple layer wiring processes, it is desirable that each layer have a smooth topography since it is difficult to lithographically image and pattern layers applied to rough surfaces. Also, rough surface topography results in poor step coverage by subsequently deposited layers, discontinuity of layers across steps, and void formation between topographic features. Poor step coverage by deposited layers and void formation between topographic features result in degraded process yield and poorer reliability in integrated circuits.
State-of-the-art processes for forming conductor-filled vias include CVD (Chemical Vapor Deposition) of tungsten into openings formed in an insulating layer. However, for large aspect ratios this process results in inclusion of voids or seams within the tungsten-filled vias and, also, requires costly and time-consuming etching or polishing steps to remove the unwanted tungsten from the surface of the insulating layer. In addition, tungsten-filled vias have relatively high resistance due to the relativley low conductivity of tungsten. Blanket deposition of other conducting materials by sputtering and other CVD processes, also, cannot produce voidless filling of vias having large aspect ratios. Plasma etching, subsequent to the filling of vias, to remove unwanted conducting material from the surface of the insulating layer is costly and time consuming because it requires a masking step. Removal of thick blanket layers of conductive material by CMP (Chemical Mechanical Polishing) is, also, costly and has unacceptable non-uniformity of removal.
Therefore, a challenge in the industry is to provide a means of formation of conducting vias between successive layers of conductive interconnection patterns, whereby the conducting via material has high electrical conductivity and is formed without voids within the vias. Also, the means of formation should have low cost and should result in smooth surface topography with the conducting via coplanar with the surrounding insulating layer.
Numerous improvements to methods of forming vias have been invented. For example, U.S. Pat. No. 5,595,943 entitled "Method for Formation of Conductor Using Electroless Plating" granted Jan. 21, 1997 to Takeyuki Itabashi et al describes electroless plating of copper from a copper plating solution which also contains an inhibitor ion, such as lead ion, silver ion, tin ion or other metal ions. The result is the copper conductor metal being deposited and filled in recessions in an insulator to the same level as the surface of the insulator. The plating reaction automatically stops when the metal conductor is formed up to the level of the surface of the insulator.
Also, U.S. Pat. No. 5,017,516 entitled "Method Of Manufacturing a Semiconductor Device" granted May 21, 1991 to Andrean M. T. P. van der Putten describes a method of electroless plating of conductive material into recesses in a dielectric layer, whereby nucleation is in a PdCl.sub.2 solution at 70.degree. C.
U.S. Pat. No. 5,595,937 entitled "Method for Fabricating Semiconductor Device with Interconnections Buried in Trenches" granted Jan. 21, 1997 to Kaoru Mikagi shows a method of forming an interconnect using a TiN/Ti film over which a Cu film is grown by a MOCVD (Metal Organic Chemical Vapor Deposition), and thereafter the films are partially removed by CMP (Chemical Mechanical Polishing).
U.S. Pat. No. 5,308,796 entitled "Fabrication of Electronic Devices by Electroless Plating of Copper onto a Metal Silicide" granted May 3, 1994 to Leonard C. Feldman et al describes a method of fabricating devices by electroless plating of copper onto a metal silicide, such as platinum or palladium silicide.